1. Field
Embodiments of the invention relate generally to a nonvolatile memory device and a method for manufacturing the same.
2. Description of the Related Art
Nonvolatile memory such as NAND flash memory is used widely for large-capacity data storage in mobile telephones, digital still cameras, USB (Universal Serial Bus) memory, silicon audio, and the like. The market continues to grow due to the reduction of manufacturing costs per bit enabled by rapid downsizing. Further, new applications are also rapidly sprouting up and lead to a virtuous cycle where downsizing and manufacturing cost reduction cultivate a new market.
In particular, NAND flash memory provides an actual crosspoint cell by a gate conductor (“GC”) line perpendicular to areas (“AA”) and is rapidly downsized due to its simple structure. Consequently, NAND flash memory leads microfabrication of semiconductor nowadays, and the minimum feature size reaches 60 nm or less even at volume production level.
However, NAND flash memory utilizes a transistor operation that records information by using a threshold voltage shift. It is considered that transistor improvements in highly-uniform characteristics, high reliability, high-speed operations, and high integration will reach a limit. The development of a new nonvolatile memory is desirable.
Under such circumstances, for example, resistance change elements or phase change memory elements operate by utilizing a variable resistance state of a resistive material. Therefore, a transistor operation is unnecessary during programming/erasing operation, and device characteristics improve as the size of the resistive material is reduced. Hence, this technology is expected to respond to future needs by achieving more-highly-uniform characteristics, higher reliability, higher-speed operations, and higher densities (for example, JP-A 2008-235637 (Kokai)).
However, memory cells including a resistance change element or the like are usually insulated from each other by an element isolation layer. These days, the space between memory cells is downsized as the downsizing of device proceeds.
Therefore, an element isolation structure of higher quality is desirable. For example, the element isolation layer preferably has a structure that does not deteriorate the memory cell, has high insulation properties, and can suppress malfunction.